Modern digital electronic circuits and systems can transmit or convey sequences of binary values, commonly referred to as bit sequences or digital signals. These bit sequences can be conveyed as voltage waveforms, wherein the voltage amplitude for a given time period or bit, corresponds to a binary logic value at that same time period. Accordingly, a digital signal can appear as a voltage waveform in the signal lines and transmission channels of electronic systems. As a digital signal is transmitted through a circuit, various effects may cause the signal to degrade, often to the point that errors occur. Errors within a digital signal may be quantified by a bit error rate. In many instances, the bit error rate of a circuit or signal pathway is defined as the ratio of incorrectly received bits to the total number of bits transmitted. An important consideration in digital electronic design is fidelity, or the quality with which a signal is conveyed. The fidelity of an electronic system is often referred to as signal integrity. As designers have increased the speed of operation and manufacturing has scaled the physical dimensions of today's modern circuits, signal integrity has become increasingly more important. Currently, virtually all electronic circuits are designed with signal integrity in mind.
Digital electronic designers often employ techniques to determine signal integrity of their designs. For example, these designers can utilize simulation tools to perform time-domain simulation on the channel to identify signal integrity problems before the device is manufactured. These simulation tools can allow the designer to account for issues that commonly cause signal degradation, such as ringing, crosstalk, noise, ground bounce, or inter-symbol interference. Time-domain simulation, however, is often time and resource intensive. From a practical standpoint, many designers can only simulate a channel for around 10,000,000 to 100,000,000 bits, which can provide a bit error rate of around 1e-7 to 1e-8, or one error every 10,000,000 to 100,000,000 bits. Current standards and reliability for channels, however, calls for bit-error rates of around 1e-12 to 1e-15, which would take four plus orders of magnitude longer to realize utilize time-domain simulation on the channel.
In an attempt to predict channel reliability in the face of the time-limitation imposed by bit-by-bit simulation, many designers implement peak distortion analysis. Peak distortion analysis often includes generation of a “worst-case input pattern” that, when input to the channel, would create a most-stressed or most-pessimistic prediction for an eye diagram associated with the channel. While this approach can allow designers to create a boundary of the eye diagram, it does not produce accurate bit error rate and creates over-pessimistic prediction of signal integrity.
Another form of channel reliability prediction is statistical simulation of the channel. Statistical simulation can determine probability distributions that describe eye-diagram, allowing predictions of the bit error rate BER as low as 1e-15 to 1e-20 bits and beyond, with minimal computational resources. Most conventional statistical simulation, however, incorporation many simplifications, such as an assumption that the channel is linear time-invariant (LTI), an assumption that jitter and noise is non-correlated, and an assumption that input bits are statistical independence, i.e. no correlation between bit-values in the input pattern. These simplifications eliminate the utilization of statistical simulation for analyzing many channels, such as those utilizing data encoding, such as 64b/66b, 128b/130b encoding, those utilizing a non-linear transmitter, and the like.